SRAM, or Static Random-Access Memory, is a type of semiconductor memory that holds each bit in a small bistable latch built from cross-coupled transistors, typically six per cell. Because the latch actively holds its state as long as power is applied, SRAM is “static”: unlike DRAM, it does not need to be periodically refreshed. This makes SRAM fast and simple to access, which is exactly why it sits at the top of the memory hierarchy.
The trade-off, as Hennessy and Patterson describe in their treatment of the memory hierarchy, is density and cost. A six-transistor SRAM cell occupies far more silicon area than a one-transistor-plus-capacitor DRAM cell, so SRAM stores far fewer bits in the same space and costs much more per bit. SRAM is therefore reserved for the places where speed matters most and capacity is small: CPU registers, the L1/L2/L3 caches, and small fast buffers inside chips.
The contrast with DRAM defines the memory hierarchy. DRAM is dense and cheap, so it forms the large main memory, but it is slower and must be refreshed. SRAM is fast and refresh-free but sparse and expensive, so it forms the caches that hide DRAM’s latency. A modern processor exploits locality of reference to keep the working set in SRAM caches and fall back to DRAM only on a miss.
Because an SRAM cell is essentially a latch, it is also the natural building block for on-chip storage that must be both fast and tightly integrated, from cache arrays to the register files at the heart of the CPU datapath. The economics of SRAM scaling — how many fast bits a process can pack onto a die — remain a central concern of processor design, since cache size strongly influences real-world performance.