The clock signal is a regular, repeating waveform, usually a square wave alternating between 0 and 1, that coordinates the parts of a synchronous digital system. Most processors and memory systems are synchronous, meaning that storage elements update their stored values only at specific instants tied to the clock, typically the rising edge where the signal transitions from 0 to 1. Between edges, combinational logic settles toward its new outputs; on the next edge, those outputs are latched into registers, and the cycle repeats. The clock therefore turns a tangle of continuously reacting gates into an orderly sequence of discrete steps.
This discipline is what makes large digital systems buildable. Combinational logic such as that analyzed in Claude Shannon’s 1937 thesis on relay and switching circuits produces outputs after some propagation delay, and different paths through a circuit take different amounts of time. By holding inputs steady for a full clock period before sampling the result, a synchronous design guarantees that every path has settled before its output is captured. The clock period must be long enough to accommodate the slowest path between two storage elements; that slowest path is what limits the clock frequency.
Clock frequency, measured in hertz, counts the cycles per second. A 1 GHz clock ticks one billion times a second, giving each combinational stage one nanosecond to settle. Through the 1990s and 2000s the pursuit of higher frequencies, the so-called gigahertz race, was a primary way to make processors faster, since more cycles per second meant more operations per second. That race eventually stalled against power and heat limits, pushing designers toward doing more work per cycle and toward multiple cores rather than ever-faster clocks.
A practical complication is clock skew: the same clock edge arrives at different parts of a chip at slightly different times because the signal travels along wires of differing length and load. If skew grows too large relative to the clock period, a register might sample a value before or after the intended moment, corrupting the computation. Distributing the clock evenly across a large chip, often through carefully balanced clock trees, is a significant engineering problem in its own right.
Conceptually, the clock is the metronome of computation. The instruction cycle of a processor, the loading of a flip-flop, and the advance of a pipeline are all timed against it. Without a shared sense of when state may change, the gates of a digital system would have no agreed moment to act, and the careful Boolean structure of the hardware would dissolve into races and glitches.