Instruction pipelining is the technique of overlapping the execution of successive machine instructions so that the processor works on several at once, each at a different stage of completion. A simple processor executes one instruction completely before starting the next: fetch it, decode it, read its operands, perform the operation, write the result. Pipelining breaks this sequence into stages and runs them like an assembly line. While one instruction is being executed, the next is being decoded, and a third is being fetched. The clock can then advance an instruction through one stage per cycle, and in steady state the machine completes one instruction every cycle even though each instruction still takes several cycles end to end.
The standard reference is Hennessy and Patterson’s textbook “Computer Architecture: A Quantitative Approach,” whose pipelining material describes the canonical five-stage integer pipeline: instruction fetch, instruction decode and register read, execute, memory access, and write back. The book frames pipelining as the foundational way processors exploit instruction-level parallelism, and it quantifies the speedup against the cost of the complications that overlap introduces.
Those complications are called hazards. A structural hazard happens when two instructions need the same hardware resource in the same cycle. A data hazard happens when an instruction needs a result that an earlier, still-in-flight instruction has not yet produced. A control hazard happens at a branch, because the processor does not yet know which instruction to fetch next. When a hazard cannot be resolved, the pipeline stalls, inserting bubbles that waste cycles. Techniques such as operand forwarding (bypassing a result straight from one stage to another) and branch prediction exist specifically to reduce these stalls.
Pipelining became central to processor design in the 1980s, especially in RISC machines, which were deliberately designed with simple, regular instructions that pipeline cleanly. The relationship is tight enough that early branch-prediction work, such as J.E. Smith’s 1981 study, was motivated explicitly by the cost of control hazards in pipelined machines: a mispredicted branch flushes the partially filled pipeline and forces it to refill, so keeping the pipeline full is a primary goal of high-performance design.
Almost every modern processor, from a microcontroller to a server CPU, is pipelined. The depth varies, from a handful of stages in a small embedded core to a dozen or more in an aggressive design, and deeper pipelines allow higher clock speeds at the cost of larger misprediction penalties. Pipelining is the base layer on which superscalar issue, out-of-order execution, and speculative execution are built.