RISC, short for Reduced Instruction Set Computer, is a design philosophy for processors that keeps the instruction set small, regular, and simple so that the hardware can be fast and the instructions can be overlapped in a pipeline. Rather than a single instruction doing a lot of work, a RISC machine favors many simple instructions, fixed-length encodings, and a load-store model in which only dedicated load and store instructions touch memory while arithmetic operates on registers.
The name and the argument come from a 1980 paper by David A. Patterson of UC Berkeley and David R. Ditzel of Bell Laboratories, “The Case for the Reduced Instruction Set Computer,” published in ACM SIGARCH Computer Architecture News. The paper proposed that the industry trend toward ever more complex instruction sets was not always cost-effective and could even do more harm than good. They argued that a carefully chosen simple instruction set, matched to the underlying architecture, could deliver high effective throughput.
The reasoning was partly economic and partly about how real programs behave. Complex instructions were often implemented in microcode and were frequently underused by compilers, while the chip area and design effort they consumed could instead go toward registers, faster cycle times, and pipelining. By stripping the instruction set down to operations a compiler would actually emit, a RISC machine could run common code faster even though each instruction did less.
The idea was made concrete by working silicon. The Berkeley RISC-I and RISC-II chips, described in papers such as Patterson and Sequin’s 1981 “RISC I: A Reduced Instruction Set VLSI Computer,” demonstrated that students could design a competitive VLSI processor around these principles. The Berkeley work investigated an alternative to the general trend toward increasingly complex instruction sets, showing that a proper instruction set with a corresponding architectural design could achieve high throughput.
RISC ideas spread quickly from research into industry. Berkeley’s work fed into Sun’s SPARC, Stanford’s parallel MIPS effort became a commercial RISC family, and the philosophy underlies the ARM cores that now ship in the overwhelming majority of phones and embedded devices. The fixed-length, load-store, pipeline-friendly style that Patterson and Ditzel argued for in 1980 became the default way to design high-performance processors.